In many memory devices, including random access memory (RAM) devices, data is typically accessed by supplying an address to an array of memory cells and then reading data from the memory cells that reside at the supplied address. However, in content addressable memory (CAM) devices, data within a CAM array is not accessed by initially supplying an address, but rather by initially applying data (e.g., search words) to the array and then performing a search operation to identify one or more entries within the CAM array that contain data equivalent to the applied data and thereby represent a “match” condition. In this manner, data is accessed according to its content rather than its address. Upon completion of the search operation, the identified location(s) containing the equivalent data is typically encoded to provide an address (e.g., block address+row address within a block) at which the matching entry is located. If multiple matching entries are identified in response to the search operation, then local priority encoding operations may be performed to identify a location of a best or highest priority matching entry. Such priority encoding operations frequently utilize the relative physical locations of multiple matching entries within the CAM array to identify a highest priority matching entry. An exemplary CAM device that utilizes a priority encoder to identify a highest priority matching entry is disclosed in commonly assigned U.S. Pat. No. 6,370,613 to Diede et al., entitled “Content Addressable Memory with Longest Match Detect,” the disclosure of which is hereby incorporated herein by reference. Additional CAM devices are described in U.S. Pat. Nos. 5,706,224, 5,852,569 and 5,964,857 to Srinivasan et al. and in U.S. Pat. Nos. 6,101,116, 6,256,216, 6,128,207 and 6,262,907 to Lien et al., assigned to the present assignee, the disclosures of which are hereby incorporated herein by reference.
CAM cells are frequently configured as binary CAM cells that store only data bits (as “1” or “0” logic values) or as ternary (or quaternary) CAM cells that store data bits and mask bits. As will be understood by those skilled in the art, when a mask bit within a ternary CAM cell is inactive (e.g., set to a logic 1 value), the ternary CAM cell may operate as a conventional binary CAM cell storing an “unmasked” data bit. When the mask bit is active (e.g., set to a logic 0 value), the ternary CAM cell is treated as storing a “don't care” (X) value, which means that all compare operations performed on the actively masked ternary CAM cell will result in a cell match condition. Thus, if a logic 0 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 1 data bit, the compare operation will indicate a cell match condition. A cell match condition will also be indicated if a logic 1 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 0 data bit. Accordingly, if a data word of length N, where N is an integer, is applied to a ternary CAM array having a plurality of entries therein of logical width N, then a compare operation will yield one or more match conditions whenever all the unmasked data bits of an entry in the ternary CAM array are identical to the corresponding data bits of the applied search word. This means that if the applied search word equals {1011}, the following entries will result in a match condition in a CAM comprising ternary CAM cells: {1011}, {X011}, {1X11}, {10X1}, {101X}, {XX11}, {1XX1}, . . . , {1XXX}, {XXXX}. As will be understood by those skilled in the art, conventional “quaternary” CAM cells, which have four valid combinations of states: ((data=0, mask=active), (data=1, mask=active), (data=0, mask=inactive), (data=1, mask=inactive)), are frequently treated as “ternary” CAM cells because two of the four states represent an equivalent active mask condition. In contrast, ternary CAM cells may include CAM cells having two bits of data that are configurable in only three valid combinations: ((0,1)=0, (1,0)=1, (0,0)=mask and (1,1)=invalid). Both types of cells will be referred to herein as ternary CAM cells.
CAM devices may also use coding techniques to detect and correct one-bit soft errors in entries within a CAM array. One such CAM device that uses a parity comparator to detect errors is described in U.S. Pat. No. 6,067,656 to Rusu et al., entitled “Method and Apparatus for Detecting Soft Errors in Content Addressable Memory Arrays.” Another such CAM device that uses dynamic content addressable memory (DCAM) cells is disclosed in U.S. Pat. No. 6,430,073 to Batson et al., entitled “DRAM CAM Cell with Hidden Refresh.” In particular, the '073 patent discloses a technique for performing hidden refresh of dynamic CAM entries using non-destructive read operations that may be performed during match line (ML) precharge operations. Upon reading, the entries may be checked for errors and possibly corrected before undergoing a refresh write operation.
U.S. Pat. No. 6,597,595 to Ichiriu et al. discloses a CAM device that performs error detection signaling operations. These error detection signaling operations are described as background error checking operations that consume little if any compare bandwidth. This is because any operation to read an entry from a CAM array for error checking purposes may be performed concurrently with the performance of compare operations on the same CAM array. As illustrated by FIG. 1, which is a reproduction of FIG. 10 from the '595 patent, a CAM array 321 is provided with multiple storage blocks 325 (shown as Blocks 1–K). In response to a read operation from a check address 155 (CADDR) within the CAM array 321, data, parity and validity values (shown as DPV1 through DPVK) are passed through a read/write circuit 322 into a parity-based error detector 323. This parity-based error detector is illustrated as including a plurality of error detection circuits 329. This check address 155 may be supplied by a check address generator (see, e.g., Block 124 in FIG. 2 of the '595 patent). Each of these error detection circuits 329 performs a parity-based error detection operation on a corresponding data word and generates a respective block parity error signal 330 (BLOCK ERROR). These block parity error signals 330 may be logically ORed by an OR gate 331 into a global parity error signal 335 (GLOBAL ERROR). The global parity error signal 335 is provided as a load input to an error address register 337 and as a set input to an S-R flip-flop 339. Whenever a block parity error is signaled by any of the error detection circuits 329, the resulting global parity error signal 335 is used to load the check address 155 into the error address register 337 and to set the S-R flip-flop 339. The S-R flip-flop 339 can be reset by driving a reset signal 153 (RESET) high. The error address register 337 is also illustrated as receiving a read signal 151 (READ) and a clock signal 104 (CLK). The error address register 337 and the S-R flip-flop 339 are configured to output an error address 131 (ERROR ADDR) and an error flag (EFLAG) 132. The error detector 323 may also include circuitry (not shown) to store a value indicative of which of the error detection circuits has signaled a block error. This value, referred to as a block identifier, may be stored along with the check address 155 in the error address register 337. The block identifier may then be output from the error address register 337 (as part of the error address) to thereby enable a host or other circuitry within the CAM device to identify the block or blocks within the CAM array 321 that produced the error indication.
Referring now to FIG. 2, which is a reproduction of FIG. 16 from the '595 patent, an alternative error detector 501 is illustrated. This error detector 501 is an error detector/corrector that uses a more complex error correction code instead of parity bit(s). At the top of FIG. 2, a CAM entry is illustrated as including a data word 503, shown as data D[M−1,0], an error correction code word 505 (e.g., Hamming code word) and a validity bit 506 (V). This CAM entry resides at the error address 536 (EADDR) specified by an ECC address generator 535. This error address 536 may be provided to an address selector (see, e.g., Block 125 in FIG. 2 of the '595 patent). As will be understood by those skilled in the art, in order to enable one bit error correction within a data word having a length of M bits, the error correction code word 505 should have a length equal to “c” bits, where the length “c” meets the following relationship: 2c≧M+c+1≧2c−1. In response to a read operation, the data word 503 and error correction code word 505 are provided to a syndrome generator 507, which generates a syndrome 508 (i.e., parity check vector). The bits of the syndrome 508 are logically ORed using an OR gate 511 to generate a result signal that indicates whether an error is present in the CAM entry. This result signal is provided to an input of a AND gate 513, which also receives the validity bit signal 506. If the CAM entry is valid (i.e., V=1), then an error signal 514 (ERROR) may be generated at the output of the AND gate 513 whenever the result signal indicates the presence of an error. An error correction circuit 509 is also provided. The error correction circuit 509 receives the data word 503 and syndrome 508. If the error represents a single bit error that can be corrected, then the error correction circuit 509 generates a C-bit signal 512 (C-BIT), which indicates whether a correction has taken place, and a corrected CAM word 510 (data word and error correction code word). At the end of each error detection operation, the error address 536 (EADDR), corrected CAM word 510 (CDATA), error signal 514 (E) and C-bit signal 512 (C) are stored within an error address register 517, which is responsive to a clock signal 104. The error signals 514 and error addresses 536 that are stored within the error address register 517 may be used to generate an error flag 532 (EFLAG) and error address 531 (EADDR), which may be used to support background self-invalidation operations (see, e.g., FIG. 14 of the '595 patent). A write data multiplexer 540, which is responsive to a path select signal 541, is also provided so that a corrected CAM word (CDATA0–CDATAx-1) may be written back into a CAM array at an address specified by the corresponding error address (EADDR0–EADDRX-1).
Notwithstanding the disclosure of the '595 patent, the performance of a background operation to read an entry from a CAM array while a foreground compare operation is being performed concurrently on the same CAM array may impact the reliability of the compare operation. This is because the performance of a read operation on a row of CAM cells within a CAM array may operate to “stress” the memory elements within the row of CAM cells and cause the logic levels of signals within the memory elements to fluctuate. Such fluctuations can represent a significant disturbances to the outputs of the memory elements, particularly if the CAM cells are powered at low voltage levels (e.g., Vdd˜1 Volt), and may result in erroneous compare operations. Accordingly, it may be more advantageous to perform read operations for error checking purposes as foreground operations that consume at least some degree of compare bandwidth.
Unfortunately, if the read operations used for error checking purposes in the error detector/corrector 501 of FIG. 2 are performed as foreground operations, then substantial compare bandwidth will likely be consumed as the ECC address generator 535 sequentially steps through the address of each CAM entry within an entire CAM core looking for errors to be corrected. To remedy this performance limitation associated with the error detector/corrector 501 of FIG. 2, a duplicate error detector/corrector 501 could be provided for each CAM storage block in the CAM core. However, unlike parity-based error detectors, which can be made relatively small, the use of an error detector/corrector 501 with each CAM storage block can be expected to consume a substantial amount of layout area and considerably increase power consumption requirements.